Unit III: Central Processing Unit (CPU) - Computer Architecture - BCA Notes (Pokhara University)

Breaking

Wednesday, April 8, 2020

Unit III: Central Processing Unit (CPU) - Computer Architecture

Computer Organization/Structure:

CPU consists of three components that are ALU, CU and Register, where ALU performs Arithmetic and Logical operation, CU provides control signals and Registers store binary information which provides fast information to ALU.

Central Processing Unit, CPU Organization/Structure, Detailed View of CPU, Register Organization, User/Programmable, Status and Control Registers, Data Paths, Functional Blocks of a Datapath, Instruction Cycle, Instruction Cycle State Diagram (Detail), Arithmetic and Logical Unit, Design Principles for Modern Systems

These all components are connected with each other and with the external environment through the system bus as shown in the figure above. The operations that must be performed by CPU are as follows:

1. Fetch Instruction: The CPU reads an information form memory.
2. Interpret Instruction: The instruction is decoded to determine what action is required.
3. Fetch Data: The execution of an instruction may require reading data from memory or an input/output module.
4. Process Data: The execution of an instruction may require performing some arithmetic or logical operations on data.
5. Write Data: The result of an execution may require writing data to memory or an input/output module.

Detailed View of CPU:

The figure shown below is a detailed view of the CPU. The data transfer and logic control path are indicated including an element labeled as internal CPU BUS. The different parts of ALU are:

1. Status Flag: It stores the status of any operation like zero, sign, overflow, etc.
2. Shifter: Performs left and right shifts.
3. Complementer: Performs bitwise operation.
4. Arithmetic and Boolean Logic: Performs arithmetic and logical operations.
5. Registers: Collection of all registers like IR, MBR, MAR, etc.

Similarly, the control unit is another important part of CPU organization, which provides control signals to all components like READ, WRITE, HALT, etc.

Central Processing Unit, CPU Organization/Structure, Detailed View of CPU, Register Organization, User/Programmable, Status and Control Registers, Data Paths, Functional Blocks of a Datapath, Instruction Cycle, Instruction Cycle State Diagram (Detail), Arithmetic and Logical Unit, Design Principles for Modern Systems

Register Organization:

Within CPU, there is a set of the register that works as an internal memory of the CPU. The number of registers set in different computers may differ. All these registers can be categorized into two groups which are as follows:

1. User/Programmable:

These registers can be used by a machine or assembly language programmer to minimize the references to the main memory. In general, there are four types of User-visible registers:

a.  General Purpose Registers (GpRs):

They are used for various functions desired by the processor. It may contain an operand or can be used for calculation of the address of operand and can even store some data.

b.  Data Register:

They are used only for storing immediate results or data. These data registers are not used for address calculation of an operand.

c.  Address Registers:

It may be any general-purpose register but in some cases, few dedicated address registers are used such as:
a. Segment Pointer: Used to point out a segment of memory.
b. Index Register: Used for index addressing scheme.
c. Stack Pointer: Used for storing an address of the top of the stack. 

d.  Flag Register:

They are also known as conditional code registers. They are used for a set or reset the condition of operation.

2. Status and Control Registers:

For control of the various operations, several registers are used. These registers cannot be used in data manipulation. Some of the important status and control registers are:
a. Program Counter: Contain address of next instruction
b. Instruction Register: Contain instruction most recently fetched.
c. Memory Address Register: Contain the address of instructions and data.
d. Memory Buffer Register: Contains a word of data to be written to memory or data word that are most recently used.

Data Paths:

A datapath is a collection of functional units (such as arithmetic logic units or multipliers, which perform data processing operations), registers, and buses. Along with the control unit, it composes the central processing unit (CPU).

During the late 1990s, there was growing research in the area of reconfigurable datapaths, which may be re-purposed at run-time using programmable fabric, as such designs may allow for more efficient processing as well as substantial power savings.

Functional Blocks of a Datapath:

In computer processors, the datapath often consists of the following functional blocks, or some variation:
a. The instruction register stores the current instruction to be executed.
b. The program counter (PC) stores the address of the next instruction to be fetched.
c. The memory address register (MAR) is a register that either store the memory address from which data will be fetched to the CPU or the address to which data will be sent and stored.
d. The memory data register (MDR) is a register of a computer's control unit that contains the data to be stored in the computer storage (e. g. RAM), or the data after a fetch from the computer storage.

There are also two registers inherent in the processor that facilitate the communication of the processor with the memory, or basically help in the memory operations of the register.

Instruction Cycle:

The basic function performed by a computer is the execution of a program which consist of a set of instruction stored in memory. The processing required for a single instruction execution is called an instruction cycle. Normally, the instruction cycle includes the following sub-cycles:
a. Fetch Cycle: Read next instruction from memory into CPU.
b. Execution Cycle: Decode the Opcode and perform the indicated operation.
c. Interrupt Cycle: If interrupts are enabled or an interrupt is executed, set the current process state and service for interrupt.

Central Processing Unit, CPU Organization/Structure, Detailed View of CPU, Register Organization, User/Programmable, Status and Control Registers, Data Paths, Functional Blocks of a Datapath, Instruction Cycle, Instruction Cycle State Diagram (Detail), Arithmetic and Logical Unit, Design Principles for Modern Systems

The execution of an instruction may involve one or more operand in memory, each of which requires memory access if indirect addressing is used then additional memory access is also required so, fetching of indirect address must be considered as extra cycle indirect execution.

Central Processing Unit, CPU Organization/Structure, Detailed View of CPU, Register Organization, User/Programmable, Status and Control Registers, Data Paths, Functional Blocks of a Datapath, Instruction Cycle, Instruction Cycle State Diagram (Detail), Arithmetic and Logical Unit, Design Principles for Modern Systems

Instruction Cycle State Diagram (Detail):

Central Processing Unit, CPU Organization/Structure, Detailed View of CPU, Register Organization, User/Programmable, Status and Control Registers, Data Paths, Functional Blocks of a Datapath, Instruction Cycle, Instruction Cycle State Diagram (Detail), Arithmetic and Logical Unit, Design Principles for Modern Systems

The figure above shown is in the form of a state diagram. For any given instruction cycle some states may be NULL and others may be visited more than once. The states can be described as follows:
1. Instruction Address Calculation: Determine the address of the next instruction to be executed. Usually, this involves adding a fixed number to the address of previous instruction.
2. Instruction Fetch: Read instruction from its memory location into the processor.
3. Instruction Operand Decoding: Analyze instruction to determine the type of operation to be performed and operations to be used.
4. Operand Address Calculation: If the operation involved reference to an operand in memory then determine the address of the operand.
5. Operand Fetch: Fetch the operand from memory or read it in the form of input/output.
6. Data Operation: Perform the operation indicated in the instruction.
7. Operand Store: Write the result into memory or out to input/output.
8. Interrupt Check: If any type of error occurs in the program then service those interrupts.

Arithmetic and Logical Unit:

An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic operations. It represents the fundamental building block of the central processing unit (CPU) of a computer. Modern CPUs contain very powerful and complex ALUs. In addition to ALUs, modern CPUs contain a control unit (CU).

Most of the operations of a CPU are performed by one or more ALUs, which load data from input registers. A register is a small amount of storage available as part of a CPU. The control unit tells the ALU what operation to perform on that data, and the ALU stores the result in an output register. The control unit moves the data between these registers, the ALU, and memory.

An ALU performs basic arithmetic and logic operations. Examples of arithmetic operations are addition, subtraction, multiplication, and division. Examples of logic operations are comparisons of values such as NOT, AND, and OR.

Central Processing Unit, CPU Organization/Structure, Detailed View of CPU, Register Organization, User/Programmable, Status and Control Registers, Data Paths, Functional Blocks of a Datapath, Instruction Cycle, Instruction Cycle State Diagram (Detail), Arithmetic and Logical Unit, Design Principles for Modern Systems

Design Principles for Modern System:

There is a set of design principles, sometimes called the RISC design principles that architects of general-purpose CPUs do their best to follow:

1. All Instructions Are Directly Executed by Hardware:
    a. Eliminates a level of interpretation

2. Maximize the Rate at Which Instructions are Issued:
    a. MIPS = millions of instructions per second.
    b. MIPS speed related to the number of instructions issued per second.
    c. Parallelism can play a role

3. Instructions Should be Easy to Decode:
    a. A critical limit on the rate of issue of instructions.
    b. Make instructions regular, fixed-length, with a small number of fields.
    c. The fewer different formats for instructions the better.

4. Only Loads and Stores Should Reference Memory:
    a. Operands for most instructions should come from- and return to- registers.
    b. Access to memory can take a long time.
    c. Thus, only LOAD and STORE instructions should reference memory.

5. Provide Plenty of Registers:
    a. Accessing memory is relatively slow, many registers (at least 32) need to be provided so            that once a word is fetched, it can be kept in a register until it is no longer needed.

No comments:

Post a Comment

If you have any doubt, then don't hesitate to drop comments.