RISC (Reduced Instruction Set Computer) is a CPU design strategy based on the insight that simplified instruction set gives higher performance when combined with a microprocessor architecture which has the ability to execute the instructions by using some microprocessor cycles per instruction.

Reduced Instruction Set Computer (RISC) - Computer Architecture

In this “Reduced Instruction Set Computer (RISC) - Computer Architecture” you will learn about following topics:

  1. Introduction to CISC and RISC Architecture
  2. CISC Architecture
  3. Characteristics of CISC Architecture
  4. Advantages of CISC Architecture
  5. Disadvantages of CISC Architecture
  6. RISC Architecture
  7. Characteristics of RISC Architecture
  8. Advantages of RISC Architecture
  9. Disadvantages of RISC Architecture
  10. RISC v/s CISC
  11. Pipelining
  12. Types of Pipeline
  13. Arithmetic Pipeline
  14. Instruction Pipelining
  15. RISC Pipelining
  16. Conflicts or Hazards in Instruction Pipelining and their Solutions
  17. Structural Hazards
  18. Solution of Structural Hazards
  19. Control Hazards
  20. Solution of Control Hazards
  21. Data Hazards
  22. Solution of Data Hazards
  23. Register Window
  24. Register Renaming




==== Point to Note ====

If you like to contribute, you can mail us BCA Notes, BCA Question Collections, BCA Related Information, and Latest Technology Information at [email protected].

See your article appearing on BCA Notes (Pokhara University) main page with your designation and help other BCA Students to excel.

Please write comments if you find anything incorrect, or you want to share more information about the topic discussed above.

BCA 5th Semester Computer Architecture Notes Pdf: